VHDL(VHSIC Hardware Description Languae)

VHDL은 디지털 회로의 설계 자동화에 사용하는 하드웨어 기술 언어이다. VHDL이라는 이름은 ‘VHSIC 하드웨어 기술 언어'(VHSIC Hardware Description Languae)의 약자이다.

VHDL는 원래 미국 국방부에서 주문형 집적회로(ASIC)의 문서화에 사용하기 위해 만든 언어였다. 즉, 복잡한 매뉴얼로 회로의 동작 내용을 설명하는 대신, 회로의 동작 내용을 문서화하여 설명하기 위해 개발했다. 그러나 이런 문서를 회로 디자인 과정에서 시뮬레이션에 사용하게 되었고, VHDL 파일을 읽어들여서 논리 합성을 한 다음 실제 회로 형태를 출력하는 기능을 덧붙이게 되었다. 오늘날에는 디지털 회로의 설계, 검증, 구현등의 모든 용도로 사용하고 있다.

VHDL은 Ada 프로그래밍 언어의 부분집합에 디지털 회로에 필수적인 시간 개념을 추가하는 방식으로 만들어졌으나, IEEE 표준화 작업을 거치면서 오늘날과 같은 형태와 문법을 가지게 되었다.

Discussion

VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.

The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.

A final point is that when a VHDL model is translated into the “gates and wires” that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being “executed” as if on some form of a processor chip.


Getting Started

As with any hardware or software language, becoming proficient in VHDL requires a commitment to study and practice. Although background in a computer programming language (such as C) is helpful, it is not essential. Today, free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user’s goal is to learn RTL coding, i.e. design hardware circuits in VHDL (as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also essential to the learning process.

As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.

Nearly all FPGA design and simulation flows support both Verilog and VHDL, allowing the user to learn either or both languages. Here is a list of free design & simulation packages for VHDL/Verilog:

Vendor Trial Software License Simulator Synthesizer RTL view Gate view
Actel Libero gold one year free license ModelSim Actel Edition Synplify Actel Edition No *yes
Altera Quartus II web edition one year free license ModelSim Altera Edition Altera Quartus II yes *yes
Lattice ispLever starter 6 months renewable free license Precision/Synplify Lattice Edition No yes
Mentor none free license ModelSim PE Student Edition no yes no
Xilinx ISE webpack free license ISE Simulator Xilinx XST yes *yes

출처: 위키백과(한글), 위키백과(영문)

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