4 Bits to BCD Code
library IEEE;
use IEEE.std_logic_1164.all;
entity bcdconv is
port ( digit_in : in std_logic_vector(3 downto 0);
bcd_out : out std_logic_vector(4 downto 0));
end bcdconv;
architecture bcdconv_arch of bcdconv is
begin
process(digit_in)
begin
if (digit_in > “1001”) then
bcd_out(4) <= ‘1’;
bcd_out(3) <= ‘0’;
bcd_out(2) <= digit_in(2) and digit_in(1);
bcd_out(1) <= not digit_in(1);
bcd_out(0) <= digit_in(0);
else
bcd_out(4) <= ‘0’;
for i in 3 downto 0 loop
bcd_out(i) <= digit_in(i);
end loop;
end if;
end process;
end bcdconv_arch;