Huffman Code는? 디지털 전송에서 평균 부호의 길이를 가장 짧게 할 수 있는 가변 길이 부호(variable length code)의 하나. 신호의 발생 빈도를 고려해서 Code를 배정하는 방법으로, 빈도수가 높으면 Code의 길이를 짧게, 빈도수가 낮으면 Code 길이를 길게 배정한다. 이렇게 배정을 하면 데이터의 손실없이 전체 크기를 줄이는 효과를 가져오게 된다. Fax나 JPEG, MPEG등 각종 정보 압축 규격으로 많이 사용되고 있다.
총 1000개의 글자가 있다고 가정하고, 글자를 3bit로 표현할 경우 총 3000bit를 필요로 한다. 하지만, Huffman code를 사용하게 되면 2180bit를 차지하므로 약 2/3로 압축된 것을 알 수 있다.
The Karnaugh map, also known as a Veitch diagram (K-map or KV-map for short), is a tool to facilitate management of Boolean algebraic expressions. A Karnaugh map is unique in that only one variable changes value between squares, in other words, the rows and columns are ordered according to the principles of Gray code.
Usage in boolean logic Normally, extensive calculations are required to obtain the minimal expression of a Boolean function, but one can use a Karnaugh map instead.
* Problem solving uses - Karnaugh maps make use of the human brain's excellent pattern-matching capability to decide which terms should be combined to get the simplest expression. - K-maps permit the rapid identification and elimination of potential race hazards, something that boolean equations alone cannot do. - A Karnaugh map is an excellent aid for simplification of up to six variables, but with more variables it becomes hard even for our brain to discern optimal patterns. - For problems involving more than six variables, solving the boolean expressions is more preferred than the Karnaugh map. Karnaugh maps also help teach about Boolean functions and minimization. Properties A mapping of minterms on a Karnaugh mapA Karnaugh map may have any number of variables, but usually works best when there are only a few - between 2 and 6 for example. Each variable contributes two possibilities to each possibility of every other variable in the system. Karnaugh maps are organized so that all the possibilities of the system are arranged in a grid form and between two adjacent boxes only one variable can change value. This is what allows it to reduce hazards.
When using a Karnaugh map to derive a minimized function, one "covers" the ones on the map by rectangular "coverings" that contain a number of boxes equal to a power of 2 (for example, 4 boxes in a line, 4 boxes in a square, 8 boxes in a rectangle, etc). Once a person has covered the ones, a term of a sum of products is produced by finding the variables that do not change throughout the entire covering, and taking a 1 to mean that variable and a 0 as the complement of that variable. Doing this for every covering gives you a matching function.
One can also use zeros to derive a minimized function. The procedure is identical to the procedure for ones except that each term is a term in a product of sums - and a 1 means the complement of the variable while 0 means the variable non-complemented.
Each square in a Karnaugh map corresponds to a minterm (and maxterm). The picture to the right shows the location of each minterm on the map.
Map The input variables can be combined in 16 different ways, so our Karnaugh map has to have 16 positions. The most convenient way to arrange this is in a 4x4 grid.
K-map showing minterms and boxes covering the desired mintermsThe binary digits in the map represent the function's output for any given combination of inputs. We write 0 in the upper leftmost corner of the map because f = 0 when A = 0, B = 0, C = 0, D = 0. Similarly we mark the bottom right corner as 1 because A = 1, B = 0, C = 1, D = 0 gives f = 1. Note that the values are ordered in a Gray code, so that precisely one variable flips between any pair of adjacent cells.
After the Karnaugh map has been constructed our next task is to find the minimal terms to use in the final expression. These terms are found by encircling groups of 1's in the map. The encirclings must be rectangular and must have an area that is a power of two (i.e. 1, 2, 4, 8, …). The rectangles should be as large as possible without containing any 0's. The optimal encirclings in this map are marked by the green, red and blue lines.
For each of these encirclings we find those variables that have the same state in each of the fields in the encircling. For the first encircling (the red one) we find that:
- The variable A maintains the same state (1) in the whole encircling, therefore it should be included in the term for the red encircling. - Variable B does not maintain the same state (it shifts from 1 to 0), and should therefore be excluded. - C does not change: it is always 0. - D changes. Thus the first term in the Boolean expression is AC'.
For the green encircling we see that A and B maintain the same state, but C and D change. B is 0 and has to be negated before it can be included. Thus the second term is AB'.
In the same way, the blue rectangle gives the term BCD' and so the whole expression is: AC' + AB' + BCD'.
논리 회로는 불 대수(논리 연산)를 실시하는 회로 또는 디지탈 신호를 기억하는 회로 혹은 두가지 기능을 가지는 디지털 회로이다.
A logic gate takes one or more logic-level inputs and produces a single logic-level output. Because the output is also a logic level, an output of one logic gate can connect to the input of one or more other logic gates.
In electronic logic, a logic level is represented by a certain voltage (which depends on the type of electronic logic in use). Each logic gate requires power so that it can source and sink currents to achieve the correct output voltage. In logic circuit diagrams the power is not shown, but in a full electronic schematic, power connections are required. There are 7 positive logic gates and each gate has two laws or rules.
논리 회로의 설계 논리 회로의 설계는 논리식이나 진리표가 사용된다. 좀더 회로도적인 표기 수단으로 MIL 기호 등 논리 소자 기호가 사용되었다.
1960년대에 등장한 표준 논리 IC (TI의 7400 시리즈)에 의하여 아날로그 회로 설계와 논리 설계를 분리하여 단순하게 구현이 가능하게 되었다.
작은 규모에서는 논리 소자 기호로 설계가 가능하지만, 큰 규모가되면 힘들어 진다. 그렇기 때문에 1990년대부터 대규모 회로 설계에는 하드웨어 기술 언어가 사용되고 있다. 그리고 집적 회로 기술의 발전에 대응할 수 있도록 다양한 모델에 적용이 가능한 독립적인 모델(동작 기술)을 사용하여 설계한다.
1990년대 후반에는 개발품의 경우 논리 회로 프로그램을 이용하여 PLD, CPLD, FPGA을 사용하였다. 양산품이나 고성능이 요구될 경우 ASIC를 사용하기도 했다. Logic gates and hardware NAND and NOR logic gates are the two pillars of logic, in that all other types of Boolean logic gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of just NAND or just NOR gate(s). They can be built from relays or transistors, or any other technology that can create an inverter and a two-input AND or OR gate. Hence the NAND and NOR gates are called the universal gates. DeMorgan equivalent symbols By use of De Morgan's theorem, an AND gate can be turned into an OR gate by inverting the sense of the logic at its inputs and outputs. This leads to a separate set of symbols with inverted inputs and the opposite core symbol. These symbols can make circuit diagrams for circuits using active low signals much clearer and help to show accidental connection of an active high output to an active low input or vice-versa.
Storage of bits Related to the concept of logic gates (and also built from them) is the idea of storing a bit of information. The gates discussed up to here cannot store a value: when the inputs change, the outputs immediately react. It is possible to make a storage element either through a capacitor (which stores charge due to its physical properties) or by feedback. Connecting the output of a gate to the input causes it to be put through the logic again, and choosing the feedback correctly allows it to be preserved or modified through the use of other inputs. A set of gates arranged in this fashion is known as a "latch", and more complicated designs that utilise clocks (signals that oscillate with a known period) and change only on the rising edge are called edge-triggered "flip-flops". The combination of multiple flip-flops in parallel, to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a sequential system since its output can be influenced by its previous state(s).
These registers or capacitor-based circuits are known as computer memory. They vary in performance, based on factors of speed, complexity, and reliability of storage, and many different types of designs are used based on the application.
불 대수(영어: Boolean algebra)는 조지 불이 19세기 중반에 고안한 논리 수학의 대표적 형태이다. 불 격자(Boolean lattice)나 불 속(束)이라고도 한다. 불 대수의 연구는 대수적 구조로서 속의 이론을 발전시키는 하나의 계기가 되었다. 수학적인 엄밀한 정의는 다음에 기술한다.
디지털 회로 설계에서는 필수적인 지식이다. 디지털 회로는 전압의 H(High), L(Low)만으로 정보를 연산하기 때문에, 기본적으로 조합 회로는 불 대수에 있는 논리식을 써서 나타낼 수 있다. (하지만, 플립 플랍 등 순차 회로는 단순하게 하나의 논리식으로 나타낼 수 없다.)
불 대수의 기본 연산(논리 연산)은 논리 부정 ¬(not), 논리합 ∨(or), 논리곱 ∧(and)로 출발된다. 이러한 연산 합성 으로부터 만들어지는 연산 중 대표적인 것으로 배타적 논리합(xor)이 있다.
불 대수를 불 격자(불 속)라고 부르는 이유는, ∨, ∧에 대해서 분배 가능한 격자가 되기 때문이다. 즉, 다음 법칙이 성립한다:
1. 멱등 법칙(idempotence): x ∧ x = x ∨ x = x, 2. 교환 법칙(commutativity): x ∧ y = y ∧ x, x ∨ y = y ∨ x, 3. 결합 법칙(associativity): (x ∧ y)∧ z = x ∧(y ∧ z), (x ∨ y)∨ z = x ∨(y ∨ z), 4. 흡수 법칙(absorption): (x ∧ y)∨ x = x, (x ∨ y)∧ x = x, 5. 분배 법칙(distributivity): (x ∨ y)∧ z = (x ∧ z)∨(y ∧ z), (x ∧ y)∨ z = (x ∨ z)∧(y ∨ z).
또한 불 대수에서는 다음 조건이 성립한다: 참을 1 거짓을 0으로 하여, 각 x 항과 반대되는 ¬x 항이 존재할 때, (x ∧ ¬x = 0), (x ∨ ¬x = 1)을 만족한다. 수학에서는 이러한 조건을 공리(公理, axiom)라 하여, 그것을 만족하는 집합을 불 격자(속)나 불 대수라고 한다.
Boolean algebra (or Boolean logic) is a logical calculus of truth values, developed by George Boole. It resembles the algebra of real numbers as taught in high school, but with the numeric operations of multiplication xy, addition x + y, and negation −x replaced by the logical operations of conjunction x∧y, disjunction x∨y, and complement ¬x. The Boolean operations are these and all other operations obtainable from them by composition; equivalently, the finitary operations on the set {0,1}. The laws of Boolean algebra can be defined axiomatically as the equations derivable from a sufficient finite subset of those laws, such as the equations axiomatizing a complemented distributive lattice or a Boolean ring, or semantically as those equations identically true or valid over {0,1}. The axiomatic approach is sound and complete in the sense that it proves respectively neither more nor fewer laws than the validity-based semantic approach. Applications Boolean algebra as the calculus of two values is fundamental to digital logic, computer programming, and mathematical logic, and is also used in other areas of mathematics such as set theory and statistics.
Digital logic codes its symbols in various ways: as voltages on wires in high-speed circuits and capacitive storage devices, as orientations of a magnetic domain in ferromagnetic storage devices, as holes in punched cards or paper tape, and so on. Now it is possible to code more than two symbols in any given medium. For example one might use respectively 0, 1, 2, and 3 volts to code a four-symbol alphabet on a wire, or holes of different sizes in a punched card. In practice however the tight constraints of high speed, small size, and low power combine to make noise a major factor. This makes it hard to distinguish between symbols when there are many of them at a single site. Rather than attempting to distinguish between four voltages on one wire, digital designers have settled on two voltages per wire, high and low. To obtain four symbols one uses two wires, and so on.
Programmers programming in machine code, assembly language, and other programming languages that expose the low-level digital structure of the data registers operate on whatever symbols were chosen for the hardware, invariably bit vectors in modern computers for the above reasons. Such languages support both the numeric operations of addition, multiplication, etc. performed on words interpreted as integers, as well as the logical operations of disjunction, conjunction, etc. performed bit-wise on words interpreted as bit vectors. Programmers therefore have the option of working in and applying the laws of either numeric algebra or Boolean algebra as needed. A core differentiating feature is carry propagation with the former but not the latter.
Other areas where two values is a good choice are the law and mathematics. In everyday relaxed conversation, nuanced or complex answers such as "maybe" or "only on the weekend" are acceptable. In more focused situations such as a court of law or theorem-based mathematics however it is deemed advantageous to frame questions so as to admit a simple yes-or-no answer---is the defendant guilty or not guilty, is the proposition true or false---and to disallow any other answer. However much of a straitjacket this might prove in practice for the respondent, the principle of the simple yes-no question has become a central feature of both judicial and mathematical logic, making two-valued logic deserving of organization and study in its own right.
A central concept of set theory is membership. Now an organization may permit multiple degrees of membership, such as novice, associate, and full. With sets however an element is either in or out. The candidates for membership in a set work just like the wires in a digital computer: each candidate is either a member or a nonmember, just as each wire is either high or low.
Algebra being a fundamental tool in any area amenable to mathematical treatment, these considerations combine to make the algebra of two values of fundamental importance to computer hardware, mathematical logic, and set theory. It has not featured so prominently in law however, perhaps because mathematical methods in general have not been applied as vigorously there as in these other application areas. Basic operations
After values, the next ingredient of any algebraic system is its operations. Whereas elementary algebra is based on numeric operations multiplication xy, addition x + y, and negation −x, Boolean algebra is customarily based on logical counterparts to those operations, namely conjunction x∧y (AND), disjunction x∨y (OR), and complement or negation ¬x (NOT).
Conjunction is the closest of these three to its numerical counterpart, in fact on 0 and 1 it is multiplication. As a logical operation the conjunction of two propositions is true when both propositions are true, and otherwise is false. The first column of Figure 1 below tabulates the values of x∧y for the four possible valuations for x and y; such a tabulation is traditionally called a truth table.
Disjunction, in the second column of the figures, works almost like addition, with one exception: the disjunction of 1 and 1 is neither 2 nor 0 but 1. Thus the disjunction of two propositions is false when both propositions are false, and otherwise is true. This is just the definition of conjunction with true and false interchanged everywhere; because of this we say that disjunction is the dual of conjunction.
Logical negation however does not work like numerical negation at all. Instead it corresponds to incrementation: ¬x = x+1 mod 2. Yet it shares in common with numerical negation the property that applying it twice returns the original value: ¬¬x = x, just as −(−x) = x. An operation with this property is called an involution. The set {0,1} has two permutations, both involutary, namely the identity, no movement, corresponding to numerical negation mod 2 (since +1 = −1 mod 2), and SWAP, corresponding to logical negation. Using negation we can formalize the notion that conjunction is dual to disjunction via De Morgan's laws, ¬(x∧y) = ¬x ∨ ¬y and ¬(x∨y) = ¬x ∧ ¬y. These can also be construed as definitions of conjunction in terms of disjunction and vice versa: x∧y = ¬(¬x ∨ ¬y) and x∨y = ¬(¬x ∧ ¬y).
Various representations of Boolean operationsFigure 2 shows the symbols used in digital electronics for conjunction and disjunction; the input ports are on the left and the signals flow through to the output port on the right. Inverters negating the input signals on the way in, or the output signals on the way out, are represented as circles on the port to be inverted.
해밍 부호(해밍符號, Hamming code)는 오류 정정 부호의 일종으로 리처드 해밍이 제안했다. 보통 해밍 부호라고 할 때는 해밍 (7,4) 부호를 가리킨다. 해밍 부호는 1비트 오류만 일어날 때는 오류를 정정할 수 있고, 2비트까지의 오류를 검출할 수 있다.
역사
해밍은 1940년대 벨 연구소에서 Bell Model V라는 컴퓨터를 이용해서 작업을 했다. 이 컴퓨터는 확실히 여러 면에서 오늘날의 컴퓨터와는 거리가 멀었다. 릴레이 회로로 만들어졌으며 입력도 천공카드를 이용했다. 천공카드를 이용했으므로 컴퓨터에 입력되는 자료들은 필연적으로 언제나 오류의 가능성이 있었다. 주중에는 컴퓨터의 관리자(operator)가 있으면서 입력에 오류가 발생했다는 경고등이 켜지면 직접 수정할 수 있었으나, 관리자가 없는 주말에는 에러가 발생한 채 프로그램이 실행되지 않고 다음 작업으로 넘어가기 일쑤였다.
해밍은 이런 문제로 인해 여러 차례 고생을 한 후에, 이 문제를 근본적으로 해결하기 위해 노력했다. 그후 몇 년 동안 오류를 수정하는 방법에 대해서 연구하면서 이와 관련된 여러가지의 효율적인 알고리즘을 만들어냈고 마침내 1950년에 해밍 부호를 발표했다. 해밍 부호는 오늘날에도 사용되고 있다.
패리티 비트
패리티 비트 (parity bit)는 주어진 비트열에 1이 짝수번 나오는지 홀수번 나오는지 추가적인 정보를 입력하는 방식이다. 예를 들어, 어떤 비트열에 1이 홀수번 나오면 패리티 비트가 1이고 짝수면 0으로 정했다고 하자. '1101011'이라는 비트열에는 1이 3번 나오므로 패리티 비트가 1이 되어서 최종적으로 11010111'이라고 쓰는 방식이다.
패리티 비트는 여러가지 단점이 있다.
짝수 개의 오류가 발생하면 하면 오류를 검출하지 못하는 경우가 생길 수 있다. 예를 들어서 '0000'을 보내려고 패리티 비트 '0'을 추가해서 '00000'을 전송했는데 오류가 발생해서 '01010'이 전송되었다고 하자. 받는 쪽에서는 1이 두번 나오므로 패리티 비트가 제대로 0으로 설정되었다고 생각할 것이고, 결과적으로 오류를 검출하지 못하게 된다. 전송된 비트열에 오류가 발생했다는 것을 알았다 하더라도 오류가 발생하기 전의 제대로 된 내용을 알 수 없다. 예를 들어서 '001000'이라는 비트열을 받았다고 하자. 이 비트열에서 1이 한 번 나오기 때문에 전송중에 오류가 생겼다는 것을 알 수 있지만, 원래 비트열은 알 수가 없다. 따라서 결과적으로 데이터를 다시 전송해야 하는 문제가 있다. 데이터의 전송 과정에서 오류가 발생하므로 패리티 비트 자체에도 오류가 생길 수 있다.
해밍 부호를 만드는 방법
2의 거듭제곱번째 위치에 있는 비트들은 패리티 비트로 사용한다. (1, 2, 4, 8, 16, 32, 64, …번째 비트) 나머지 비트에는 부호화될 데이터가 들어 간다. (3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, …번째 비트)
진성반도체란 불순물을 첨가하지 않은 순수한 반도체를 가르킨다. 영국말 intrinsic semiconductor 로부터 I형 반도체라고도 한다.
특징
캐리어 밀도 도핑된 경우는 도펀트의 밀도로 정재지는 캐리어밀도이지만, 진성 반도체는 불순물 밀도가 아니고 재질자체가 캐리어 밀도를 결정한다. 이 캐리어 밀도를 진성 캐리어 밀도 (ni)라고 한다. 이 진성 캐리어 밀도는 매우 낮은 값 (～1010 /cm3)이다. 이것은 일반적인 도핑으로 얻을 수 있는 캐리어 밀도보다 약 10 자리수만큼 낮은값이기 때문에 일반적인 반도체를 사용하는 경우는 도핑을 하는 경우가 많다.
페르미 준위 도핑된 경우에 페르미준위는 도너 준위나 억셉터 준위 근처에 존재하지만, 진성 반도체는 띠간격의 띠 중앙에 위치한다.
캐리어 이동도 진성 반도체는 불순물의 도핑이 되지 않았기 때문에 캐리어는 이온화 불순물 산란의 영향을 받지 않는다. 그렇기에 도핑되었을 때와 비교해서 매우 빠른 이동도를 나타낸다. 하지만 이전에 말했듯이 진성 반도체는 캐리어 밀도가 매우 낮기때문에 용도또한 한정된다. 탄소구조에 의한 이차원 전자 가스 를 이용한 반도체소자 (예시 HEMT)가 있다. 도핑 진성 반도체는 캐리어 밀도가 낮기때문에 일반적으로는 진성 반도체에 불순물을 도핑한 불순물 반도체 (외인성 반도체)가 사용된다. 불순물 반도체는 도너나 억셉터의 열여기에 의한 캐리어가 전도에 기여한다. 캐리어가 홀 (전공)인 P형 반도체와 캐리어가 전자인 N형 반도체로 크게 구별된다. 캐리어의 종류는 불순물의 최외각 전자의 수에 의하여 결정되며 최외각 전자가 4보다 크면 N형 반도체, 최외각 전자가 4보다 작으면 P형 반도체가 된다. 실리콘에서 인, 비소를 도핑했을 때는 N형 반도체, 붕소를 도핑했을 때는 P형 반도체가 된다.
불순물반도체는 반도체의 한 종류이다. 외인성 반도체 (영어: extrinsic semiconductor)라고도 한다. 순수한 진성반도체에 불순물 (도펀트)를 소량첨가 (도핑)한 것이다. 도핑하는 원소에 의하여 캐리어가 홀 (정공)인 P형 반도체, 캐리어가 전자인 N형 반도체를 얻을 수 있다.
캐리어의 종류는 불순물 원소의 최외각전자수에 의존적이며, 최외각전자가 4보다 클 경우는 N형 반도체, 최외각전자가 4보다 작을 경우는 P형 반도체가 된다. 반도체의 한종류인 규소를 예로 들면, 비소, 인의 경우에는 N형 반도체, 붕소의 경우에는 P형 반도체가 된다.
이진화 십진법(Binary-coded decimal, BCD)은 십진법 숫자를 이진법으로 표현된 비트들의 연속으로 표현하는 방법으로, 하나의 십진법 자리가 네 개의 이진법 자리에 곧바로 대응하므로 변환이나 역변환이 쉽다는 이점을 갖고 있다. 그러나 쓰이지 않고 버려지는 패턴이 많고 연산을 위해서 더 많은 처리와 회로가 필요하다는 단점이 있다.
이진화 십진법은 특히 숫자의 십진 출력을 요하는 전자 회로와 마이크로프로세서에서 많이 사용되는데, 이는 순수 이진법으로 표현된 숫자를 십진법으로 출력하기 위해서는 복잡한 나눗셈 회로가 필요하기 때문이다. 이진화 십진법을 사용할 경우 각 자리 별로 하나씩 간단한 변환 회로를 만들어서 7세그먼트 표시 장치 등에 바로 연결할 수 있기 때문에 전체적인 구현을 간편하게 할 수 있다. 이 때문에 일부 프로세서는 아예 BCD로 덧셈과 뺄셈 등의 간단한 연산을 할 수 있는 명령을 갖추고 있다.
규칙 이진화 십진법에서 십진법의 각 자리는 다음 표에 따라 네 개의 비트로 변환된다. 역변환도 동일하다.
많은 컴퓨터가 8비트를 묶어서 1바이트로 처리하기 때문에, 이런 환경에서 이진화 십진법을 저장하는 방법은 두 가지가 있을 수 있다.
* 한 바이트에 한 자리만을 저장하고, 남는 네 자리를 0000이나 1111(EBCDIC의 경우), 또는 0011(ASCII의 경우) 등으로 채운다. * 한 바이트에 두 자리를 저장한다.
In computing and electronic systems, Binary-coded decimal (BCD) is an encoding for decimal numbers in which each digit is represented by its own binary sequence. Its main virtue is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations. Its drawbacks are the increased complexity of circuits needed to implement mathematical operations and a relatively inefficient encoding – 6 wasted patterns per digit. Even though the importance of BCD has diminished [citation needed], it is still widely used in financial, commercial, and industrial applications.
In BCD, a digit is usually represented by four bits which, in general, represent the values/digits/characters 0-9. Other bit combinations are sometimes used for sign or other indications.
Basics To BCD-encode a decimal number using the common encoding, each decimal digit is stored in a four-bit nibble.
Thus, the BCD encoding for the number 127 would be: 0001 0010 0111
Since most computers store data in eight-bit bytes, there are two common ways of storing four-bit BCD digits in those bytes:
* each digit is stored in one byte, and the other four bits are then set to all zeros, all ones (as in the EBCDIC code), or to 0011 (as in the ASCII code) * two digits are stored in each byte.
Unlike binary encoded numbers, BCD encoded numbers can easily be displayed by mapping each of the nibbles to a different character. Converting a binary encoded number to decimal for display is much harder involving integer multiplication or divide operations. The BIOS in many PCs keeps the date and time in BCD format, probably for historical reasons (it avoided the need for binary to ASCII conversion).
In mathematics, negative numbers in any base are represented in the usual way, by prefixing them with a "−" sign. However, on a computer, there are various ways of representing a number's sign. This article deals with four methods of extending the binary numeral system to represent signed numbers: sign-and-magnitude, ones' complement, two's complement, and excess-N.
For most purposes, modern computers typically use the two's-complement representation, but other representations are used in some circumstances. Sign-and-magnitude
One may first approach this problem of representing a number's sign by allocating one sign bit to represent the sign: set that bit (often the most significant bit) to 0 for a positive number, and set to 1 for a negative number. The remaining bits in the number indicate the magnitude (or absolute value). Hence in a byte with only 7 bits (apart from the sign bit), the magnitude can range from 0000000 (0) to 1111111 (127). Thus you can represent numbers from −12710 to +12710 once you add the sign bit (the eighth bit). A consequence of this representation is that there are two ways to represent 0, 00000000 (0) and 10000000 (−0). Decimal −43 encoded in an eight-bit byte this way is 10101011.
This approach is directly comparable to the common way of showing a sign (placing a "+" or "−" next to the number's magnitude). Some early binary computers (e.g. IBM 7090) used this representation, perhaps because of its natural relation to common usage. (Many decimal computers also used sign-and-magnitude.) Ones' complement
Alternatively, a system known as ones' complement can be used to represent negative numbers. The ones' complement form of a negative binary number is the bitwise NOT applied to it — the complement of its positive counterpart. Like sign-and-magnitude representation, ones' complement has two representations of 0: 00000000 (+0) and 11111111 (−0).
As an example, the ones' complement form of 00101011 (43) becomes 11010100 (−43). The range of signed numbers using ones' complement in a conventional eight-bit byte is −12710 to +12710.
To add two numbers represented in this system, one does a conventional binary addition, but it is then necessary to add any resulting carry back into the resulting sum. To see why this is necessary, consider the following example showing the case of the addition of −1 (11111110) to +2 (00000010).
In the previous example, the binary addition alone gives 00000000—not the correct answer! Only when the carry is added back in does the correct result (00000001) appear.
This numeric representation system was common in older computers; the PDP-1 and UNIVAC 1100/2200 series, among many others, used ones'-complement arithmetic.
(A remark on terminology: The system is referred to as "ones' complement" because the negation of x is formed by subtracting x from a long string of ones. Two's complement arithmetic, on the other hand, forms the negation of x by subtracting x from a single large power of two.)
The IPv4 header checksum uses ones' complement arithmetic, here even on two's complement machines the inconvenience of having to add back a carry is a desirable error-checking property, because "it is equally sensitive to errors in all bit positions". In the UDP protocol one of the two representations of 0 provided by the ones' complement arithmetic is used for indicating that the optional checksum feature has been omitted (all 0s), whereas the other (all 1s) indicates a checksumming result of 0.
Note that the ones' complement representation of a negative number can be obtained from the sign-magnitude representation merely by bitwise complementing the magnitude.
Two's complement (http://en.wikipedia.org/wiki/Twos_complement) The problems of multiple representations of 0 and the need for the end-around carry are circumvented by a system called two's complement. In two's complement, negative numbers are represented by the bit pattern which is one greater (in an unsigned sense) than the ones' complement of the positive value.
In two's-complement, there is only one zero (00000000). Negating a number (whether negative or positive) is done by inverting all the bits and then adding 1 to that result. Addition of a pair of two's-complement integers is the same as addition of a pair of unsigned numbers (except for detection of overflow, if that is done). For instance, a two's-complement addition of 127 and −128 gives the same binary bit pattern as an unsigned addition of 127 and 128, as can be seen from the above table.
한글 P채널과 N채널의 MOSFET을 상호 보완하여 연결한 집적 회로의 구조이다. TTL 논리 소자와 비교해서 소비전력이 적은 논리 회로를 구현할수 있고, 집적도를 향상시키는것이 가능하다.
MOSFET의 동작 영역에서 직류 전달 특성은 선형 영역에서 출력 전압이 입력 전압과 거의 같고 포화 영역에서 출력 전압은 게이트 전압에서 「문턱 전압」을 뺀 값이 된다. P-MOSFET가 포화 영역일때 N-MOSFET는 선형 영역이고, N-MOSFET가 포화 영역일때 P-MOSFET는 선형 영역이다. 시모스의 동작 영역의 대부분은 선형 영역이다. 엄밀하게 양자의 「문턱 전압」이 겹치는 영역이 존재기 때문에 사용하지 않는 입력 단자는 「문턱 전압」영역에 들어가지 않도록 풀업 또는 풀다운에 연결해 주는것이 좋다.
시모스 구조로 하면 게이트 전압에 입력되는 제어 펄스를 "1"에서 "0"으로 변경했을 경우에 노이즈 없이 이전의 출력을 할수 있고, "0"에서 "1"로 변경했을 경우 역시 노이즈 없이 입력 신호를 출력할 수 있다.
시모스 구조의 논리 회로는 전원 전압을 낮게 하면 소비 전력이 적은 반면 전달 지연 시간이 커지는 특성을 가지고 있다. 제조 프로세서의 개선에 의하여 저전압 동작과 고속 동작을 할 수 있게 되었다.
1990년대가 되면서 반도체 메모리나 마이크로프로세서의 논리 IC는 대부분 시모스 구조가 되었으며 , 소규모 전원 회로, 아날로그-디지털 변환회로, 디지털-아날로그 변환회로등을 포함되어서 제작하기 시작하였다. 영문 Complementary metal–oxide–semiconductor (CMOS) ("see-moss", IPA: ['si.mɜs]), is a major class of integrated circuits. CMOS technology is used in chips such as microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication.
CMOS is also sometimes explained as complementary-symmetry metal–oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions.
Two important characteristics of CMOS devices are high noise immunity and low static power supply drain. Significant power is only drawn when its transistors are switching between on and off states; consequently, CMOS devices do not produce as much heat as other forms of logic such as TTL (transistor-transistor logic). CMOS also allows a high density of logic functions on a chip.
The triple compound "metal–oxide–semiconductor" is a reference to the nature of the physical structure of early (and interestingly now, the very latest) field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. Instead of metal, current gate electrodes (including those up to the 65 nanometer technology node) are almost always made from a different material, polysilicon, but the terms MOS and CMOS nevertheless continue to be used for the modern descendants of the original process. (See also MOSFET.) Metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS transistor as announced by IBM and Intel for the 45 nanometer node and beyond.
The combination of MEMS sensors with digital signal processors on one single CMOS chip is sometimes known an CMOSens.
VHDL은 디지털 회로의 설계 자동화에 사용하는 하드웨어 기술 언어이다. VHDL이라는 이름은 'VHSIC 하드웨어 기술 언어'(VHSIC Hardware Description Languae)의 약자이다.
VHDL는 원래 미국 국방부에서 주문형 집적회로(ASIC)의 문서화에 사용하기 위해 만든 언어였다. 즉, 복잡한 매뉴얼로 회로의 동작 내용을 설명하는 대신, 회로의 동작 내용을 문서화하여 설명하기 위해 개발했다. 그러나 이런 문서를 회로 디자인 과정에서 시뮬레이션에 사용하게 되었고, VHDL 파일을 읽어들여서 논리 합성을 한 다음 실제 회로 형태를 출력하는 기능을 덧붙이게 되었다. 오늘날에는 디지털 회로의 설계, 검증, 구현등의 모든 용도로 사용하고 있다.
VHDL은 Ada 프로그래밍 언어의 부분집합에 디지털 회로에 필수적인 시간 개념을 추가하는 방식으로 만들어졌으나, IEEE 표준화 작업을 거치면서 오늘날과 같은 형태와 문법을 가지게 되었다.
Discussion
VHDL is a fairly general-purpose language, although it requires a simulator on which to run the code. It can read and write files on the host computer, so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Because of this general-purpose nature, it is possible to use VHDL to write a testbench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected. This is similar to the capabilities of the Verilog language. VHDL is a strongly typed language, and as a result is considered by some to be superior to Verilog. In fact there has always been quite an intense debate which amounts to a holy war amongst developers over which is the superior language. However, both languages make it easy for the unwary and inexperienced to produce code that simulates successfully, but that cannot be synthesized into a real device, or else is too large to be practicable. A particular pitfall in both languages is the accidental production of transparent latches rather than D-type flip-flops as storage elements.
The key advantage of VHDL when used for systems design is that it allows the behaviour of the required system to be described (modelled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system (many parts, each with its own sub-behaviour, working together at the same time). This is unlike many of the other computing languages such as BASIC, Pascal, C, or lower-level assembly language which runs at machine code level, which all run sequentially, one instruction at a time on von Neumann architectures.
A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.
Getting Started
As with any hardware or software language, becoming proficient in VHDL requires a commitment to study and practice. Although background in a computer programming language (such as C) is helpful, it is not essential. Today, free VHDL simulators are readily available, and although these are limited in functionality compared to commercial VHDL simulators, they are more than sufficient for independent study. If the user's goal is to learn RTL coding, i.e. design hardware circuits in VHDL (as opposed to simply document or simulate circuit behavior), then a synthesis/design package is also essential to the learning process.
As with VHDL simulators, free FPGA synthesis tools are readily available, and are more than adequate for independent study. Feedback from the synthesis tool gives the user a feel for the relative efficiencies of different coding styles. A schematic/gate viewer shows the user the synthesized design as a navigable netlist diagram. Many FPGA design packages offer alternative design input methods, such as block-diagram (schematic) and state-diagram capture. These provide a useful starting template for coding certain types of repetitive structures, or complex state-transition diagrams. Finally, the included tutorials and examples are valuable aids.
Nearly all FPGA design and simulation flows support both Verilog and VHDL, allowing the user to learn either or both languages. Here is a list of free design & simulation packages for VHDL/Verilog:
코일이란 유도 계수를 사용하기 위해서 전선을 감은 수동 소자이다. 인덕터(영어: Inductor)나 선륜(낡은 말투)이라고도 한다. 전자 유도에 의한 자력선을 사용하기 위해 전선으로 감은것을 권선이라고 한다.
Physics
- Overview
Inductance (measured in henries) is an effect which results from the magnetic field that forms around a current-carrying conductor. Electrical current through the conductor creates a magnetic flux proportional to the current. A change in this current creates a change in magnetic flux that, in turn, generates an electromotive force (emf) that acts to oppose this change in current. Inductance is a measure of the generated emf for a unit change in current. For example, an inductor with an inductance of 1 henry produces an emf of 1 V when the current through the inductor changes at the rate of 1 ampere per second. The number of turns, the area of each loop/turn, and what it is wrapped around affect the inductance. For example, the magnetic flux linking these turns can be increased by coiling the conductor around a material with a high permeability.
- Stored energy
The energy (measured in joules, in SI) stored by an inductor is equal to the amount of work required to establish the current flowing through the inductor, and therefore the magnetic field. This is given by:
where L is inductance and I is the current flowing through the inductor.
- Hydraulic model Electrical current can be modeled by the hydraulic analogy. The inductor can be modeled by the flywheel effect of a turbine rotated by the flow. As can be demonstrated intuitively and mathematically, this mimics the behavior of an electrical inductor; voltage is proportional to the derivative of current with respect to time. Thus a rapid change in current will cause a big voltage spike. Likewise, in cases of a sudden interruption of water flow the turbine will generate a high pressure across the blockage, etc. Magnetic interactions such as in transformers are not usefully modeled hydraulically.
종류 - 공심 코일 전선을 원통형태로 감아서 원통 내부가 비어 있거나 베이클라이드같은 비자성체로 전선을 보관 유지하는 코일이다. 내구력이 크고 유도 계수가 작기 때문에 주로 고주파용으로 사용된다. 주위의 물체나 코일의 간격(피치)로 인하여 유도 계수가 변동되기 쉽다. 그리고 원형판 주위에 홀수각으로 깍아서 전선을 감은 평면상의 코일이 있으며 이것은 거미집의 형태와 비슷해서 스파이더 코일이라고 불린다. - 코어 코일 막대기형, E자형, 북모양 같은 코어(철심)에 권선을 감은 코일이다. 코일의 재질은 페라이트를 이용하는 것이 많다. 저항기와 같은 직선 모양의 양단에 리드선이 나와있는 코일의 형식이 있으며, 이를 마이크로 인덕터라 불린다. 고주파용 코일은 원통형 보빈(영어: bobbin)에 전선을 감아서 내부 코어를 드라이버로 움직여서 유도 계수를 조정하는 것도 있다. 대전류 전원 회로는 변압기와 같은 규소강판도 사용되며 이를 초크 코일이라고 부른다.
코어에 사용되는 재질은 다음과 같은 종류가 있다. * 페라이트 * 더스트 코어… 압축 자심재라고도 한다. 금속을 분말로 만들어서 절연 처리후 가압 성형한 것 카보닐 철 Fe(CO)5 몰리브덴 파마 로이（몰리브덴, 니켈, 철） 센다스트（규소、알루미늄、철）
- 트로이달 코일(링 코일) 도너츠형의 강자성체에 권선을 감은 코일이다.이것에 이용하는 도너츠형의 코어를 토로이달 코어라 불리며 단독으로 시판되고 있다. 코어의 투자율(透磁率)에 의해서 구분된 권수와 유도 계수의 관계를 나타내는 도표는 제조사에서 공개하고 있다. 코일의 권수는 도너츠 구멍을 지나는 전선수를 의미한다. 주위 물체의 영향을 받지 않고 누설 자속이 적으며 유도 계수의 안정성 및 재성성이 높아서 고주파 회로에 널리 사용된다.
1. 와이브로(WiBro:Wireless Broadband) 무선으로 이동중에 휴대전화처럼 쉽게 사용할 수 있는 무선광대역 인터넷 서비스기술을 뜻한다. 한국의 통신 업체들이 정부의 지원을 받아 함께 개발하고 있으며, 국제 표준화도 추진중에 있다. 현재 한국내 사업자로 KT와 SK텔레콤이 선정되었고, 2006년 6월 30일 일부지역에서 세계 최초로 상용화 서비스가 시작 되었다. 처음엔 고속 데이터 통신 기술을 지칭하는 용어로 고안된 것이지만 통신업체에 의해 서비스되는 전국 액세스망으로 선보일 예정으로 기술 이름보다 서비스 명으로 더 잘 알려질 것이다. HSDPA 가 다운로드 중심이라면 와이브로는 업로드를 특화한 기술이라 할 수 있다. 인텔에서 추진중인 무선 광대역 인터넷 서비스 WiMAX와도 호환성 개선을 위해 노력중이다.
WiBro is a wireless broadband Internet technology being developed by the Korean telecoms industry. It adapts TDD for duplexing, OFDMA for multiple access and 8.75 MHz as a channel bandwidth. WiBro was devised to overcome the speed limitation of mobile phone (for example CDMA 1x) and to add mobility to broadband Internet (for example ADSL or Wireless LAN). In February 2002, the Korean government allocated 100 MHz of electromagnetic spectrum in the 2.3 - 2.4 GHz band, and in late 2004 WiBro Phase 1 was standardized by the TTA of Korea and in late 2005 ITU reflected WiBro as IEEE 802.16e (mobile WiMAX). WiBro is the service name for mobile WiMAX in Korea. Two Korean Telco (KT, SKT) launched commercial service in June 2006, and the tariff is around 30 US$. WiBro base stations will offer an aggregate data throughput of 30 to 50 Mbit/s and cover a radius of 1-5 km allowing for the use of portable internet usage. In detail, it will provide mobility for moving devices up to 120 km/h (74.5 miles/h) compared to Wireless LAN having mobility up to walking speed and Mobile Phone having mobility up to 250 km/h. From testing during the APEC Summit in Busan in late 2005, the actual range and bandwidth were quite a bit lower than these numbers. The technology will also offer Quality of Service. The inclusion of QoS allows for WiBro to stream video content and other loss-sensitive data in a reliable manner. These all appear to be (and may be) the stronger advantages over the fixed WiMAX standard (802.16a). Some Telcos in many countries are trying to commercialize this Mobile WiMAX (or WiBro). For example, TI (Italia), TVA (Brazil), Omnivision (Venezuela), PORTUS (Croatia), andArialink (Michigan) will provide commercial service after test service around 2006-2007. While WiBro is quite exacting in its requirements from spectrum use to equipment design, WiMAX leaves much of this up to the equipment provider while providing enough detail to ensure interoperability between designs. 2. WiMAX(Worldwide Interoperability for Microwave Access) WiMAX is defined as Worldwide Interoperability for Microwave Access by the WiMAX Forum, formed in June 2001 to promote conformance and interoperability of the IEEE 802.16 standard, officially known as WirelessMAN. WiMAX aims to provide wireless data over long distances, in a variety of different ways, from point to point links to full mobile cellular type access. In practical terms this enables a user, for example, to browse the Internet ona laptop computer without physically connecting the laptop to a wall jack. The Forum describes WiMAX as "a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL."
The bandwidth and reach of WiMAX make it suitable for the following potential applications:
□ Connecting Wi-Fi hotspots with each other and to other parts of the Internet. □ Providing a wireless alternative to cable and DSL for last mile (last km) broadband access. □ Providing high-speed data and telecommunications services. □ Providing a diverse source of Internet connectivity as part of a business continuity plan. That is, if a business has a fixed and a wireless Internet connection, especially from unrelated providers, they are unlikely to be affected by the same service outage. □ Providing nomadic connectivity.
고속 하향 패킷 접속 [高速下向-接續, high speed downlink packet access]
비동기식 3세대 이동 통신의 하향 링크에서 10Mbps 수준의 고속 패킷 데이터 서비스를 제공하는 전송 규격. 인터넷 통신은 주로 내려받기(download)가 많아 하향 링크의 고속화가 서비스의 필수 요소이며, 고속 데이터는 주로 정지 상태에서 사용되므로 이러한 조건을 최대한 수용하도록 하향 링크의 전송 규격을 개선한 것으로 WCDMA R5에 적용되었다. 기본 개념은 각종 물리 링크나 MAC 링크 기능을 기지국에서 수행하도록 하며, 단말기가 기지국에 가깝거나 정지 상태에서는 오버헤드를 줄여 처리 속도를 높인 것으로, 적응 변조 및 코딩(AMC), 하이브리드 자동 재송 요구(HARQ), 송수신 다중 다이버시티(multiple input multiple output), 고속 패킷 스케줄링 등의 기술이 적용되었다.
High-Speed Downlink Packet Access (HSDPA) (Sometimes known as High-Speed Downlink Protocol Access) is a 3G mobile telephony protocol in the HSPA family, which provides a roadmap for UMTS-based networks to increase their data transfer speeds and capacity. Current HSDPA deployments now support 1.8 Mbit/s, 3.6 Mbit/s, 7.2 Mbit/s and 14.4 Mbit/s in downlink. Further speed grades are planned for the near future. The networks are then to be upgraded to HSPA Evolved, which provides speeds of 42Mbit downlink in its first release. In addition to supporting high data speeds, HSDPA greatly increases the capacity of the network. Current HSDPA networks have the capacity to provide each customer with 30 gigabytes of data per month in addition to 1000 minutes of voice and 300 minutes of mobile TV.
Adoption As of March 19 2007, 100 HSDPA networks have commercially launched mobile broadband services in 54 countries. Near to 40 HSDPA networks support 3.6 Mbps peak data throughput (downlink direction). A growing number are delivering 7.2 Mbps peak data throughput, leveraging new higher-speed devices coming into the market. One network has been declared as “14.4 Mbps (peak) ready” while several additional networks will have this capability by end 2007. The first commercial HSUPA (uplink direction) network is launched, with several more set to follow in 2007. This protocol is a relatively simple upgrade where UMTS is already deployed. CDMA-EVDO networks had the early lead on performance, and Japanese and South Korean providers were the highly successful benchmark for that technology. Lately the situations seems to be changing in favour of HSDPA as an increasing number of providers worldwide are adopting it. South Korea's KTF and SK Telecom built nationwide HSDPA networks. KTF are selling HSDPA handsets to its customers on March 2007. SK Telecom announcing that by first half of 2007 it will be selling HSDPA handsets to its customers and that it will be cutting funding to its CDMA2000 network. A similar situation occurred in Australia, with Telstra announcing the closure of its CDMA-EVDO network and its replacement with a HSDPA network.
Technology The HS-DSCH channel does away with two basic features of other W-CDMA channels—the variable spreading factor and fast power control—and instead uses
1. Adaptive Modulation and Coding (AMC), 2. fast packet scheduling at the Node B (Base Station), and 3. fast retransmissions from Node B (known as HARQ-Hybrid Automatic Repeat Request)
to deliver the improved downlink performance. The concept of "incremental redundancy" is used in HARQ, where retransmissions contain different codings of the user data, relative to the original transmission. When a corrupted packet is received, the user device saves it, and combines it with subsequent retransmissions, to formulate an error-free packet as quickly and efficiently as possible. Even if the retransmitted packet(s) is itself corrupted, the combination of the sum of the errored transmissions can yield an error-free packet.
Fast Packet Scheduling The HS-DSCH downlink channel is shared between users using channel-dependent scheduling to take advantage of favourable channel conditions to make best use of available radio conditions. Each user device periodically transmits (as often as 500 times per second) an indication of the downlink signal quality. The Node B uses this information received from all user devices to decide which users will be sent data on the next 2 ms frame and, for each user, how much data should be attempted. More data can be sent to users which report high downlink signal quality.
The amount of the channelisation code tree, and thus network bandwidth, allocated to HSDPA users is determined by the network. The allocation is "semi-static" in that it can be modified while the network is operating, but not on a frame-by-frame basis. This allocation represents a tradeoff between bandwidth allocated for HSDPA users, versus that for voice and non-HSDPA data users. The allocation is in units of channelisation codes for Spreading Factor 16, of which 16 exist, and of which up to 15 can be allocated to HSDPA.
When the Node B decides which users will receive data on the next 2 ms frame, it also determines which channelisation code(s) will be employed for each user, and this information is sent to the user devices over one or more HSDPA "scheduling channels" (these scheduling channels are not part of the HSDPA allocation previously mentioned, but are allocated separately). Thus, for a given 2 ms frame, data may be sent to a number of users simultaneously, using different channelisation code. The maximum number of users to receive data on a given 2 ms frame is determined by the number of allocated channelisation codes. This differs from CDMA2000 1xEV-DO, where data is sent to only one user at a time.
Adaptive Modulation and Coding The modulation scheme and coding is changed on a per-user basis depending on signal quality and cell usage.
QPSK is the initial modulation scheme, however, in good radio conditions the introduction of 16QAM modulation will improve data throughput rates by approximately double that of QPSK. QPSK with 5 Code allocation will typically offer up to 1.8 Mbit/s peak data rates. 16QAM with 5 Codes will increase this to 3.6 Mbit/s. Additional Codes (e.g. 10, 15) can also be used to improve these data rates or extend the network capacity throughput significantly. Theoretically, HSDPA can give throughput up to 10.8 Mbit/s.
Other Improvements HSDPA is part of the UMTS standards from release 5 onwards, which also accompanies an improvement on the uplink providing a new bearer of 384 kbit/s (previous max bearer was 128 kbit/s).
As well as improved data rates that are associated with HSDPA one of the key benefits that are seen is the reduction on latency, improving the round trip time for applications.
Along with the HS-DSCH channel, three new physical channels are also introduced. One is the High Speed-Shared Control CHannel (HS-SCCH) which informs the user that data will be sent on the HS-DSCH 2 slots ahead. The second one is the Uplink High Speed-Dedicated Physical Control CHannel (HS-DPCCH), which carries acknowledgment information and current channel quality indicator (CQI) of the user. This value is then used by the Node-B in calculating how much data to send to the UE on the next transmission. The third downlink physical channel is the HS-PDSCH (High Speed-Physical Downlink Shared CHannel). This is the physical channel mapped to the above HS-DSCH transport channel that carries actual user data.
A phasor is a constant complex number representing the complex amplitude (magnitude and phase) of a sinusoidal function of time. (In older texts, a phasor is alternatively referred to as a sinor.) It is usually expressed in exponential form. Phasors are used in engineering to simplify computations involving sinusoids, where they can often reduce a differential equation problem to an algebraic one.
A sinusoid (or sine waveform) is defined to be a function of the form (the reason for using cosine rather than sine will become apparent later)
where
- y is the quantity that is varying with time - Ф is a constant (in radians) known as the phase or phase angle of the sinusoid - A is a constant known as the amplitude of the sinusoid. It is the peak value of the function. - ω is the angular frequency given by ω = 2πf where f is frequency. - t is time.
This can be expressed as
where
- j is the imaginary unit . Note that i is not used in electrical engineering as it is commonly used to represent the changing current. - gives the real part of the complex number z
Equivalently, by Euler's formula,
Y, the phasor representation of this sinusoid is defined as follows:
such that
Thus, the phasor Y is the constant complex number that encodes the amplitude and phase of the sinusoid. To simplify the notation, phasors are often written in angle notation:
Within Electrical Engineering, the phase angle is commonly specified in degrees rather than radians and the magnitude will often be the rms value rather than a peak value of the sinusoid.
The overarching conceptual motive behind phasor calculus is that it is generally far more convenient to manipulate complex numbers than to manipulate literal trigonometric functions. Noting that a trigonometric function can be represented as the real component of a complex quantity, it is efficacious to perform the required mathematical operations upon the complex quantity and, at the very end, take its real component to produce the desired answer. This is quite similar to the concept underlying complex potential in such fields as electromagnetic theory, where—instead of manipulating a real quantity, u—it is often more convenient to derive its harmonic conjugate, v, and then operate upon the complex quantity u + jv, again recovering the real component of the complex "result" as the last stage of computation to generate the true result.
Circuit laws
With phasors, the techniques for solving DC circuits can be applied to solve AC circuits. A list of the basic laws is given below.
Ohm's law for resistors: a resistor has no time delays and therefore doesn't change the phase of a signal therefore V=IR remains valid.
Ohm's law for resistors, inductors, and capacitors:V=IZ where Z is the complex impedance.
In an AC circuit we have real power (P) which is a representation of the average power into the circuit and reactive power (Q) which indicates power flowing back and forward. We can also define the complex power S=P+jQ and the apparent power which is the magnitude of S. The power law for an AC circuit expressed in phasors is then S=VI* (where I* is the complex conjugate of I).
Kirchhoff's circuit laws work with phasors in complex form
Given this we can apply the techniques of analysis of resistive circuits with phasors to analyse single frequency AC circuits containing resistors, capacitors, and inductors. Multiple frequency linear AC circuits and AC circuits with different waveforms can be analysed to find voltages and currents by transforming all waveforms to sine wave components with magnitude frequency and phase then analysing each frequency separately. However this method does not work for power as power is based on voltage times current.
반도체(半導體)는 열 등의 에너지를 통해 전도성을 급격하게 변화시킬 수 있는 고체물질이다. 일반적으로 많이 사용되는 것은 실리콘(4족 원소)의 결정에 불순물을 넣어서 만든다. 반도체를 이용해 집적회로를 만들어 증폭장치, 계산장치 등에 이용한다.
반도체는 매우 낮은 온도에서는 부도체처럼 동작하고, 실온에서는 상당한 전도성을 지닌다. 물론 도체와는 차이가 있다. 절대 0도에서 차 있는 가장 윗부분의 전자 에너지 밴드가, 반도체의 경우에는 가득 차 있고, 도체의 경우에는 일부만 차 있다. 이에 반해 반도체와 부도체의 차이점은 임의적이다. 반도체는 에너지 띠간격(bandgap)이 충분히 작기 때문에, 실온에서 전자가 쉽게 전도띠(conduction band)로 올라갈 수 있다. 그에 반해, 부도체는 띠간격이 커서 전자가 전도띠로 잘 올라가지 못한다.
반도체의 띠구조
고체물리학에서, 반도체란 ‘절대 0도에서 가장 위의 가전자대(valence band, 원자가띠; 차 있는 전자 에너지 상태의 가장 위의 에너지 띠)가 완전히 차 있는 고체’로 정의된다. 다르게 말하자면, 전자의 페르미 에너지가 금지된 띠(forbidden bandgap)에 있는 것을 말한다. (절대 0도에서 전자 상태가 어느 수준까지만 차 있게 되는데, 이를 페르미 에너지, 혹은 페르미 준위라고 한다) 실온에서는 전자 분포가 조금 흐트러지는 현상이 발생한다. 물론 조금이긴 하지만, 무시할 수 없는 만큼의 전자가 에너지 띠간격을 넘어서 전도띠로 간다. 전도띠로 갈만큼 충분한 에너지를 가지고 있는 전자는 이웃하고 있는 원자와의 공유결합을 끊고, 자유롭게 이동할 수 있는 상태가 돼서 전하를 전도시킨다. 이렇게 전자가 뛰쳐나온 공유결합은 전자가 부족해지게 된다. (또는 자유롭게 이동할 수 있는 구멍(양공)이 생겼다고도 볼 수 있다. 구멍은 사실 그 자체가 움직이는 것은 아니지만, 주변의 전자가 움직여서 그 구멍을 메우면 구멍이 그 전자가 있던 자리로 옮겨간 것처럼 보인다. 이런 식으로 구멍이 이동하는 것처럼 보인다.) 도체와 반도체의 중요한 차이점은, 반도체에서는 전류가 흐르는 경우 전자와 양공이 모두 이동한다는 것이다. 이와 달리 금속은 페르미 준위가 전도띠 안에 있기 때문에 그 전도띠는 일부만 전자로 채워진다. 이 경우에는 전자가 다른 비어있는 상태로 이동하기 위해 필요한 에너지가 적고, 그래서 전류가 잘 흐른다. 반도체의 전자가 가전자대에서 전도띠로 얼마나 쉽게 이동하는지는 그 띠 사이의 띠간격에 달려있다. 그리고 이 에너지 띠간격의 크기가 반도체와 부도체를 나누는 기준이 된다. 보통 띠간격 에너지가 3 eV이하인 물질은 반도체로 간주하고, 이보다 큰 경우에는 부도체로 간주한다. 물질에서 전류를 흐르게 하는 전자는 보통 그냥 "전자"라고 하지만, 정식 명칭은 "자유전자"이다. 가전자대의 양공(전자가 떠난 자리에 남는 구멍)은 마치 전자에 대응되는 양전하 입자(positively- charged particle)같은 성질을 띤다. 그래서 보통 양공을 실제로 대전된 입자로 간주한다.
P-N 접합
반도체에 P형과 N형 도펀트를 인접하게 도핑하면 PN 접합을 만들 수 있다. P형으로 도핑된 부분에 +바이어스 전압을 걸어주면, P형 반도체의 다수 운반자(양공)가 접합면 쪽으로 밀려간다. 동시에 N형 반도체의 다수 운반자(전자)도 접합면 쪽으로 끌려간다. 그러면 접합면에는 운반자가 많아져서, 접합면이 도체 같은 성질을 띠게 되고, 접합면에 걸려있는 전압 때문에 전류가 흐른다. 양공 구름(양공이 구름처럼 몰려있는 것)과 전자구름이 만나면, 전자가 그 구멍(양공)으로 들어가서 움직이지 않는 공유결합을 이룬다. 만약 바이어스 전압이 반대로 걸리면, 양공과 전자는 접합면으로부터 서로 밀어낸다. 접합면에서는 새로운 전자/홀 쌍(pair)이 잘 생기지 않기 때문에, 접합면 주위에 있던 운반자는 모두 쓸려가버리면서, 접합면 주위에 운반자가 거의 없는 고갈영역을 형성하게 된다. (전자는 +전압이 걸려있는 N영역 쪽으로, 양공은 -전압이 걸려있는 P영역 쪽으로 쓸려간다) 역방향 바이어스 전압은 접합면에 전류가 아주 조금만 흐르게 한다. P-N접합은 전류가 한쪽 방향으로만 흐르게 하는 다이오드라는 소자의 원리이다. 비슷한 원리로, 세 번째 반도체 영역은 N형이나 P형으로 도핑해서 단자가 3개 있는 소자를 만들 수 있다. 이렇게 만들어낸 소자가 BJT(bipolar junction transistor)이다. 이 BJT는 P-N-P로 만들 수도 있고, N-P-N으로 만들 수도 있다.
엠파스 경제사전 - 용어설명 통화자 개개인의 음성 및 영상 정보를 디지털로 바꿔 고유의 코드를 부여해 전송할 수 있는 차세대 이동통신 기술이다. 협대역 CDMA는 주파수대역이 1.25MHz지만, 광대역은 5-15MHz로 넓다.이는 1차선 도로와 4-8차선 고속도로의 차이로서 그만큼 광대역으로는 멀티미디어 정보를 많이 초고속으로 보낼 수 있다. 우리나라가 새로운 시내전화방식으로 검토하고 있는 무선가입자망(WLL)분야에도 적용 할 수 있어 상용화에 성공할 경우 상당한 규모의 수입대체는 물론 해외시장 진출 효과를 거둘 수 있을 것으로 전망된다.
W-CDMA is a type of 3G cellular network. W-CDMA is the higher speed transmission protocol used in the Japanese FOMA system and in the UMTS system, an advanced 3G system, designed as a replacement for the aging 2G GSM networks deployed worldwide.
More technically, W-CDMA is a wideband spread-spectrum mobile air interface that utilizes the direct sequence Code Division Multiple Access signalling method (or CDMA) to achieve higher speeds and support more users compared to the older TDMA signalling method of GSM networks. W-CDMA is a competitor to CDMA2000.
Technical features -Radio channels are 5MHz wide. -Chip rate of 3.84 Mcps -Supports two basic modes of duplex, frequency division and time division. Current systems use frequency division, one frequency for uplink and one for downlink. For time division, FOMA uses sixteen slots per radio frame, where as UMTS uses 15 slots per radio frame. -Employs coherent detection on uplink and downlink based on the use of pilot symbols. -Supports inter-cell asynchronous operation. -Variable mission on a 10 ms frame basis. -Multicode transmission. -Adaptive power control based on SIR (Signal-to-Interference Ratio). -Multiuser detection and smart antennas can be used to increase capacity and coverage. -Multiple types of handoff between different cells including soft handoff, softer handoff and hard handoff.
Development W-CDMA was developed by NTT DoCoMo as the air interface for their 3G network FOMA. Later NTT DoCoMo submitted the specification to the International Telecommunication Union (ITU) as a candidate for the international 3G standard known as IMT-2000. The ITU eventually accepted W-CDMA as part of the IMT-2000 family of 3G standards, as an alternative to CDMA2000, EDGE, and the short range DECT system. Later, W-CDMA was selected as the air interface for UMTS, the 3G successor to GSM.
Code Division Multiple Access communication networks have been developed by a number of companies over the years, but development of cell-phone networks based on CDMA (prior to W-CDMA) was dominated by Qualcomm, the first company to succeed in developing a practical and cost-effective CDMA implementation for consumer cell phones, its early IS-95 air interface standard. IS-95 evolved into the current CDMA2000 (IS-856/IS-2000) standard.
In the late 1990s, NTT DoCoMo began work on a new wide-band CDMA air interface for their planned 3G network FOMA. FOMA's air interface, called W-CDMA, was selected as the air interface for UMTS, a newer W-CDMA based system designed to be an easier upgrade for European GSM networks compared to FOMA. FOMA and UMTS use essentially the same air interface, but are different in other ways; thus, handsets are not 100% compatible between FOMA and UMTS, but roaming is supported.
Qualcomm created an experimental wideband CDMA system called CDMA2000 3x which unified the W-CDMA (3GPP) and CDMA2000 (3GPP2) network technologies into a single design for a worldwide standard air interface. Compatibility with CDMA2000 would have beneficially enabled roaming on existing networks beyond Japan, since Qualcomm CDMA2000 networks are widely deployed, especially in the Americas, with coverage in 58 countries in 2006. However, divergent requirements resulted in the W-CDMA standard being retained and deployed.
Despite incompatibilities with existing air-interface standards, the late introduction of this 3G system, and despite the high upgrade cost of deploying an all-new transmitter technology, W-CDMA has been adopted and deployed rapidly, especially in Japan, Europe and Asia, and is already deployed in over 55 countries with ????? subscribers in 2006.[1]
Rationale for W-CDMA W-CDMA transmits on a pair of 5 Mhz wide radio channels, while CDMA2000 transmits on one or several pairs of 1.25 MHz radio channels. Though W-CDMA does use a direct sequence CDMA transmission technique like CDMA2000, W-CDMA is not simply a wideband version of CDMA2000. The W-CDMA system is a new design by NTT DoCoMo, and it differs in many respects from CDMA2000. From an engineering point of view, W-CDMA provides a different balance of costs vs. capacity vs. performance vs. density, and promises to achieve a benefit of reduced cost for video phone handsets. W-CDMA may also be better suited for deployment in the very dense cities of Europe and Asia. And cross-licencing of patents between Qualcomm and W-CDMA vendors has eliminated possible patent issues due to the features of W-CDMA which remain covered by Qualcomm patents.
W-CDMA has been developed into a complete set of specifications, a detailed protocol that defines how a mobile phone communicates with the tower, how signals are modulated, how datagrams are structured, and system interfaces are specified allowing free competition on technology elements.
A resistive circuit is a circuit containing only resistors, ideal current sources, and ideal voltage sources. This means that relationships between current and voltage are linear. If the sources are constant (DC) sources, the result is a DC circuit. The analysis of a circuit refers to the process of solving for the voltages and currents present in the circuit. The solution principles outlined here also apply to phasor analysis of AC circuits.
Two electric circuits are said to be equivalent with respect to a pair of terminals if the voltages across the terminals and currents through the terminals are identical for both networks.
If V2 = V1 implies I2 = I1 for all (real) values of V1, then with respect to terminals ab and xy, circuit 1 and circuit 2 are equivalent.
Resistors in series and in parallel
Resistors in series:
Resistors in parallel:
The above simplified for only two resistors in parallel:
1. Label all nodes in the circuit. Arbitrarily select any node as reference. 2. Define a voltage variable from every remaining node to the reference. These voltage variables must be defined as voltage rises with respect to the reference node. 3. Write a KCL equation for every node except the reference. 4. Solve the resulting system of equations.
(Mesh — a loop that does not contain an inner loop.) 1. Count the number of “window panes” in the circuit. Assign a mesh current to each window pane. 2. Write a KVL equation for every mesh whose current is unknown. 3. Solve the resulting equations
Choice of method
Given the choice, which method should be used: nodal analysis or mesh analysis?
Nodal analysis: The number of voltage variables equals number of nodes minus one. Every voltage source connected to the reference node reduces the number of unknowns by one.
Mesh analysis: The number of current variables equals the number of meshes. Every current source in a mesh reduces the number of unknowns by one.
There is also another point to consider: mesh analysis only applies to planar circuits, i.e. circuits that can be drawn using only two dimensions. Intuitively, what this means is that the wires in the circuit diagram must not "jump over" one another if one is to apply mesh analysis. Nodal analysis, on the other hand, can be applied to both planar and non-planar circuits. Note that sometimes, a circuit that is drawn in a non-planar fashion (i.e. with wires jumping over each other) may be redrawn in planar form, although this is not always the case. Generally, most of the circuits one encounters in elementary resistive network analysis are planar in nature.
To summarize, for planar circuits, either nodal or mesh analysis may be used; generally, the method with the least unknowns to solve for is selected. For circuits that are non-planar, one can try to redraw the circuit in planar form; if this is not possible, one has no choice but to apply nodal analysis.
A resistor is a two-terminal electrical or electronic component that resists an electric current by producing a voltage drop between its terminals in accordance with Ohm's law.: The electrical resistance is equal to the voltage drop across the resistor dividedby the current through the resistor. Resistors are used as part of electrical networks and electronic circuits.
The Ideal resistor
The SI unit of electrical resistance is the ohm (Ω). A component has a resistance of 1 Ω if a voltage of 1 volt across the component results in a current of 1 ampere, or amp, which is equivalent to a flow of one coulomb of electrical charge (approximately 6.241506 × 1018 electrons) per second. The multiples kiloohm (1 kΩ = 1000 Ω) and megaohm (1 MΩ = 106 Ω) are also commonly used. In an ideal resistor, the resistance remains constant regardless of the applied voltage or current through the device or the rate of change of the current. Whereas real resistors cannot attain this goal, they are designed to present little variation in electrical resistance when subjected to these changes, or to changing temperature and other environmental factors.
Four-band axial resistors
Four-band identification is the most commonly used color coding scheme on all resistors. It consists of four colored bands that are painted around the body of the resistor. The scheme is simple: The first two numbers are the first two significant digits of the resistance value, the third is a multiplier, and the fourth is the tolerance of the value. Each color corresponds to a certain number, shown in the chart below. The tolerance for a 4-band resistor will be 2%, 5%, or 10%. The Standard EIA Color Code Table per EIA-RS-279 is as follows:
Color
1st band
2nd band
3rd band (multiplier)
4th band (tolerance)
Temp. Coefficient
Black
×10
Brown
1
1
×101
±1% (F)
100 ppm
Red
2
2
×102
±2% (G)
50 ppm
Orange
3
3
×103
15 ppm
Yellow
4
4
×104
25 ppm
Green
5
5
×105
±0.5% (D)
Blue
6
6
×106
±0.25% (C)
Violet
7
7
×107
±0.1% (B)
Gray
8
8
×108
±0.05% (A)
White
9
9
×109
Gold
×0.1
±5% (J)
Silver
×0.01
±10% (K)
None
±20% (M)
Note: red to violet are the colors of the rainbow where red is low energy and violet is higher energy. Resistors use specific values, which are determined by their tolerance. These values repeat for every exponent; 6.8, 68, 680, and so forth. This is useful because the digits, and hence the first two or three stripes, will always be similar patterns of colors, which make them easier to recognize.
5-band axial resistors
5-band identification is used for higher tolerance resistors (1%, 0.5%, 0.25%, 0.1%), to notate the extra digit. The first three bands represent the significant digits, the fourth is the multiplier, and the fifth is the tolerance. 5-band standard tolerance resistors are sometimes encountered, generally on older or specialized resistors. They can be identified by noting a standard tolerance color in the 4th band. The 5th band in this case is the temperature coefficient.
발광 다이오드는 순방향으로 전압을 가했을 때 발광하는 반도체 소자이다. LED (한국어: 엘이디, 영어: Light Emitting Diode)라고도 불리며, 발광 원리는 전계 발광 (영어: Electroluminescence) 효과를 이용하고 있다. 또한 수명도 백열전구보다 상당히 길다.
발광색은 사용되는 재료에 따라서 다르며 자외선영역에서 가시광선, 적외선 영역까지 발광하는 것을 제조할 수 있다. 일리노이 대학의 닉 호로니악에 의하여 1962년에 최초로 개발되었다. 오늘까지 여러가지 용도로 사용되었으며 향후 형광등이나 전구를 대체할 광원으로 기대되고 있다.
원리 발광 다이오드는 반도체를 이용한 PN 접합이라고 불리는 구조로 만들어져 있다. 발광은 PN 접합에서 전자가 가지는 에너지를 직접 빛 에너지로 변환되어, 거시적으로는 열이나 운동에너지를 필요로 하지 않는다. 전극으로부터 반도체에 주입된 전자와 정공은 다른 에너지띠 (전도띠나 원자가띠)를 흘러 PN 접합부 부근에서 띠간격를 넘어 재결합한다. 재결합할 때 거의 띠간격에 상당한 에너지가 광자, 즉 빛으로 방출된다. 전기적 특성 다른 일반적인 다이오드와 동일하게 극성을 가지고 있으며, 캐소드 (음극)에서 애노드 (양극)로 정전압을 가해서 사용한다. 전압이 낮은 동안은 전압을 올려도 거의 전류가 흐르지 않고, 발광도 하지 않는다. 어느 전압 이상이 되면 전압 상승에 대하여 전류가 빠르게 흘러서, 전류량에 비례해서 빛이 발생된다. 이 전압을 순방향 강하전압이라고 하고, 일반적인 다이오드와 비교해서 발광 다이오드는 순방향 강하전압이 높다. 발광색에 따라 다르지만, 빨간색, 오렌지색, 노란색, 초록색에서는 2.1V 정도이다. 빨간빛을 내지 않는 것은 1.4V 정도이다. 백색과 파란색은 3.5V 정도이다. 고출력 제품은 5V 전후인것도 있다.
발광할 때 소비 전류는 표시등 용도에서는 수 mA ~ 50 mA정도 이지만, 조명 용도에서는 소비 전력이 수W단위의 대출력 발광 다이오드도 판매되고 있어 구동 전류가 1 A 를 넘는 제품도 있다.
역방향으로 전압을 가하는 경우의 내전압은 일반적인 실리콘 다이오드 보다 더 낮고, 보통은 -5 V 정도이며, 이것을 넘으면 소자가 파괴된다. 따라서, 정류 용도로 사용할 수 없다.
광학적 특성 형광등이나 백열등같은 다른 대다수 광원과 다르게 불필요한 자외선이나 적외선을 포함하지 않는 빛을 간단하게 얻을 수 있다. 그렇기 때문에 자외선에 민감한 문화재나 예술 작품이나 열조사를 꺼리는 물건의 조명에 사용된다. 입력 전압에 대한 응답이 빨라서 통신에도 사용되고, 조명으로 사용할 경우는 점등하자마자 최대 빛의 세기를 얻을 수 있다.
재료 발광되는 빛의 파장 (색)은 PN 접합을 형성하는 소재의 띠간격의 크기와 관련있다. 발광 다이오드는 근적외선이나 가시광선, 자외선에 이르는 파장에 대응하는 띠간격을 가지는 반도체 재료가 이용된다. 일반적으로 발광 다이오드에는 발광재결합 확률이 높은 직접 천이형의 반도체가 적합하고, 일반적인 반도체 재료인 규소 (실리콘)나 게르마늄같은 간접 천이형 반도체에서는 전자나 정공이 재결합할 경우에 빛을 방출하기 어렵다. 그러나 노란색이나 황녹색에 오랫동안 사용되어온 GaAsP계나 GaP계는 도핑한 불순물 준위를 개입시켜 강한 발광을 하는 재료도 있어서 넓게 사용되고 있다.
아래의 소재를 사용하여 다양한 색의 발광 다이오를 만들 수 있다.
알루미늄 갈륨 비소 (AlGaAs) - 적외선, 빨간색 갈륨 비소 인 (GaAsP) - 빨간색, 오랜지색, 노란색 인듐 질화 갈륨 (InGaN)／질화 갈륨 (GaN)／알루미늄 질화 갈륨 (AlGaN) - （오랜지색, 노란색）녹색, 파란색, 보라색, 자외선 인화 갈륨 (GaP) - 빨간색, 노란색, 녹색 셀렌화 아연 (ZnSe) - 녹색, 파란색 알루미늄 인듐 갈륨 인 (AlGaInP) - 오랜지색, 노란색, 녹색 다이아몬드 (C) - 자외선 산화 아연(ZnO) - 근 자외선 (개발중) 아래는 기판으로 사용되고 있다.
사용자의 인증을 목적으로 휴대 전화 사용자의 개인 정보 (통신 사업자와 사용자 패스워드, 로밍 정보, 사용자의 개인 전화번호)를 저장하는 모듈로서 스마트 카드(USIM 카드)로 제작된다.
USIM 카드는 휴대가 간편하여 단말기 종류나 통신 사업자에 구애받지 않고 국제 로밍을 포함한 음성 이동 전화와 전자 상거래 서비스를 활용할 수 있게 한다. 또한 스마트 카드의 강력한 보안 기능으로 휴대 전화를 분실하거나 교체하였을 경우 개인 정보의 보호가 가능할 뿐만 아니라, 보안 등이 요구되는 지불 및 인증 기능을 제공함으로써 콘텐츠 유료 서비스의 구매 등 그 활용 범위가 매우 넓다.
USIM 카드는 우리나라를 비롯한 부호 분할 다중 접속(CDMA) 서비스권에서는 일반적으로 사용하지 않으나, 유럽 등 전 지구적 이동 통신 시스템(GSM) 서비스권에서는 USIM 카드와 유사한 가입자 인식 모듈(SIM) 카드를 많이 사용하고 있다.
국제 이동 통신-2000(IMT-2000) 서비스가 개시되면 우리나라에서도 USIM 카드를 활발히 사용할 것으로 보이며 전자 상거래, 신용 카드, 금융 결제 등 일반 생활에 커다란 영향을 미칠 것으로 예상된다.
gives the real part of the complex number z
