Category: HDL

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Carry Look-ahead Adder Design

Carry Look-ahead Adder(캐리 예측 덧셈기) 전가산기를 이용한 Ripple Carry Adder는 많은 bit의 연산을 하려고 할 때지연되는 시간이 길어지는 단점을 갖는다. CLA(Carry Look-ahead Adder)의 경우는 carry의 발생을 bit입력시바로 계산하여 시간의 지연...

2’s compliment & Absolute Unit 0

2’s compliment & Absolute Unit

[code]`timescale 1ns / 1ps//////////////////////////////////////////////// 2’s Complement, Absolute Unit Design////////////////////////////////////////////////2’s Complement Unitmodule twos_com(ref_data_8bit,com_out);   input [7:0] ref_data_8bit; // 8bit input unsigned number   output [15:0] com_out;  // 16bit output signed number  ...

4-Bit Ripple Carry Adder 0

4-Bit Ripple Carry Adder

[code] `timescale 1ns / 1ps // 4Bit Ripple Carry Adder // 4bit Ripple Carry Adder module module FBit_RCA(i_a, i_b, c_in, o_sum, c_out);  // Inputs  input [3:0] i_a, i_b;...

10 input-4 output Encoder 0

10 input-4 output Encoder

                     <ABEL CODE> module E10x4BCD;title ’10 inputs to 4 outputs – BCD Encoder’;Enc10x4 device ‘P22V10’; “Input pinsI0,I1,I2,I3,I4,I5,I6,I7,I8,I9 pin 2,3,4,5,6,7,8,9,10,11;“output...

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4 Bits to BCD Code

library IEEE;use IEEE.std_logic_1164.all;entity bcdconv is    port ( digit_in : in std_logic_vector(3 downto 0);    bcd_out : out std_logic_vector(4 downto 0));end bcdconv;architecture bcdconv_arch of bcdconv isbegin    ...

PGM for 74×49 (7 segments decoders) 0

PGM for 74×49 (7 segments decoders)

        <ABEL CODE> module SSEGDECtitle ‘asdfas’SEGDEC device ‘P22V10’;“input pins!BL pin 2;D,C,B,A pin 3,4,5,6;“output pinsOa,Ob,Oc,Od,Oe,Of,Og pin 23,22,21,20,19,18,17;Out = [Oa,Ob,Oc,Od,Oe,Of,Og];equationswhen (!BL==1) then Oa = (!A&!C)#(A&B&!D)#(A&C&!D)#(B&C&D)#(!A&D)#(!B&!C&D);when (!BL==1) then...

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VHDL integer와 std_logic_vector 사이의 변환

library IEEE;use IEEE.Std_Logic_arith.all;use IEEE.Std_Logic_1164.all;entity conv is    port ( input : in std_logic_vector (7 downto 0);   — std_logic_vector 입력과 integer 입력           input_i :...