Tagged: 논리회로

2’s compliment & Absolute Unit 0

2’s compliment & Absolute Unit

[code]`timescale 1ns / 1ps//////////////////////////////////////////////// 2’s Complement, Absolute Unit Design////////////////////////////////////////////////2’s Complement Unitmodule twos_com(ref_data_8bit,com_out);   input [7:0] ref_data_8bit; // 8bit input unsigned number   output [15:0] com_out;  // 16bit output signed number  ...

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5-Phase Shifter

< 간략한 설명 >74×163을 이용하여 Master Clock Edge L->H Trigger 2번을다시 새로운 클럭으로 생성하고, 이 클럭에 의해 74×194를 동작시킴.(이렇게 하는 이유는 단순히 문제이기 때문에…)그 다음부터는 5-Phase Shifter으로써 동작하며...

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VHDL integer와 std_logic_vector 사이의 변환

library IEEE;use IEEE.Std_Logic_arith.all;use IEEE.Std_Logic_1164.all;entity conv is    port ( input : in std_logic_vector (7 downto 0);   — std_logic_vector 입력과 integer 입력           input_i :...

ABEL – Prime number detector 0

ABEL – Prime number detector

<ABL 코드>module pdetectortitle ‘4 bit prime number detecting code by changkyu’PDETECT device ‘P16V8C’; “input pinsN0, N1, N2, N3 pin 2,3,4,5; “output pinsF pin 19; “definitionNUM = [N3, N2,...

ABEL – 2×4 decoder 0

ABEL – 2×4 decoder

<ABL 코드>module decoder2to4title ‘2 to 4 decoder abel code by changkyu’DCODER device ‘P16V8C’; “input pinsI0, I1 pin 2,3;EN pin 4; “output pinsY0, Y1, Y2, Y3 pin 16,17,18,19; “constantsX...

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Karnaugh map – 카노 맵

The Karnaugh map, also known as a Veitch diagram (K-map or KV-map for short), is a tool to facilitate management of Boolean algebraic expressions. A Karnaugh map is...