VHDL integer와 std_logic_vector 사이의 변환
library IEEE;use IEEE.Std_Logic_arith.all;use IEEE.Std_Logic_1164.all;entity conv is port ( input : in std_logic_vector (7 downto 0); — std_logic_vector 입력과 integer 입력 input_i :...
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library IEEE;use IEEE.Std_Logic_arith.all;use IEEE.Std_Logic_1164.all;entity conv is port ( input : in std_logic_vector (7 downto 0); — std_logic_vector 입력과 integer 입력 input_i :...