Source Follower Design
< 설계 조건 >* VDD=1.8V, Power budget = 1.8mW * Voltage gain = 0.9* Min. allowable output = 0.3V(VDS2≥0.3V 일 때 M2는 saturation)* λ = 0.1 V-1...
Monthly Archive: 3월 2009
2’s compliment & Absolute Unit
[code]`timescale 1ns / 1ps//////////////////////////////////////////////// 2’s Complement, Absolute Unit Design////////////////////////////////////////////////2’s Complement Unitmodule twos_com(ref_data_8bit,com_out); input [7:0] ref_data_8bit; // 8bit input unsigned number output [15:0] com_out; // 16bit output signed number ...
키보드 특수기호 이름
` Grave ‘~ Tilde ! Exclamation Point @ At Sign ...
4-Bit Ripple Carry Adder
[code] `timescale 1ns / 1ps // 4Bit Ripple Carry Adder // 4bit Ripple Carry Adder module module FBit_RCA(i_a, i_b, c_in, o_sum, c_out); // Inputs input [3:0] i_a, i_b;...
